XXIIVV

Notes on Ternary Logic.

Along with ternary arithmetic, a computer built of ternary hardware can also exploit ternary logic. Consider the task of comparing two numbers. In a machine based on binary logic, comparison is often a two-stage process. First you ask, "Is x less than y?"; depending on the answer, you may then have to ask a second question, such as "Is x equal to y?" Ternary logic simplifies the process: A single comparison can yield any of three possible outcomes: "less," "equal" and "greater."

Single Input Gates

The gate names uses the heptavintimal notation.

Reversible Gates

To learn more, see reversible computing.

+0-NumberNameDefinitions
0----13FalseNEG(LAX(LAX))
A--0-12NEG(LAX)
B--+-11Decoder(-)DEC(DEC(LAX))
C-0--10AbnNEG(LAX(DEC))
D-00-9DEC(LAX(NEG))
E-0+-8NegationNEG
F-+--7Decoder(0)DEC(DEC(LAX(DEC)))
G-+0-6IncrementDEC(DEC)
H-++-5DEC(NEG(LAX(NEG)))
I0---4NEG(LAX(NEG))
J0-0-3DEC(LAX(DEC))
K0-+-2DecrementDEC
L00--1DEC(LAX)
M0000ClearDEC(LAX(LAX))
N00+1NEG(DEC(LAX))
O0+-2NEG(DEC)
P0+03NEG(DEC(LAX(DEC)))
Q0++4LAX(NEG)
R+--5Floor/Decoder(+)DEC(DEC(LAX(NEG)))
S+-06DEC(NEG)
T+-+7DEC(NEG(LAX(DEC)))
U+0-8IdentityNEG(NEG)
V+009FlatNEG(DEC(LAX(NEG)))
W+0+10AbsLAX(DEC)
X++-11CeilDEC(NEG(LAX))
Y++012LaxLAX
Z+++13TrueLAX(LAX)
AND B
F U T
A F F F F
U F U U
T F U T
OR B
F U T
A F F U T
U U U T
T T T T
Inputs Outputs
X Y TNAND TNOR
−1 −1 1 1
−1 0 1 0
−1 1 1 −1
0 −1 1 0
0 0 0 0
0 1 0 −1
1 −1 1 −1
1 0 0 −1
1 1 −1 −1