Assembly languages have a strong correspondence between the operands and the architecture.

Subleq is a One Instruction Set Computer(OISC) architecture.

The Subleq instruction subtracts the contents at address a from the contents at address b, stores the result at address b, and if the result is negative or zero, jumps to address in c. If the result is positive, execution proceeds to the next instruction.

if (mem[B] -= mem[A]) <= 0 
	goto C

Each Subleq instruction is stored in 3 cells, each cell holds a number. For example, to add two numbers, 3 and 4, stored in cells 0x9 and 0xa.

0 0 0 3   m[0] - m[0], m[0] = 0, jump to 3.
3 9 0 6   m[0] - m[9], m[0] = -3, jump to 6.
6 0 a 0   m[a] - m[0], m[a] = 7..
9 3 4 0 

Interpreter

Subleq programs can be encoded in Uxntal and evaluated. Here is an example program that adds to numbers and copies the result into a specific cell:

Jump(Q)

&0 -&0 -&0 -/Q
&Q 

Adding(x,y)

&0 -&0 -&0 -/1
&1 -&x -&0 -/2
&2 -&0 -&y -/Q

&x 12
&y 34
&Q

Move(x,y)

&0 -&0 -&0 -/1
&1 -&y -&y -/2
&2 -&x -&0 -/3
&3 -&0 -&y -/4
&4 -&0 -&0 -/Q

&a 12
&Q

BranchOnEqual(b,c)

&0   -&0 -&0 -/1
&1   -&b -&0 -/L1
&2   -&0 -&0 -/OUT
&L1  -&0 -&0 -/4
&4   -&0 -&b -/c
&OUT ..
&b
&c
&Q

• Oleg Mazonka

One of the most famous esolangs.

Brainfuck operates on an array of memory cells, each initially set to zero. A pointer is initially pointing to the first memory cell. All characters that are no operations should be ignored, and considered to be comments.

Interpreter

Memory should normally consist of 8 bit cells, and wrap on overflow and underflow. Negative memory addresses should NOT be assumed to exist, however, an interpreter may provide some. Memory should consist of at least 30000 cells, some existing brainfuck programs do need more so this should be configurable or unbounded.

Evaluation

Evaluation consists of moving along the memory an incrementing or decrementing the value stored in the 8-bit cells.

+++  Store 3 at 0
>>   Move to 2
+    Store 1 at 2

Loop

A simple loop is a matter of decrementing a counter in a cell:

+++++ Store 5 at 0
[-]   Decrement

IO

The output operator emits the ASCII value at the cell.

++++++++
++++++++
++++++++
++++++++
++++++++
.        Write 0x28, or '('

Compiler

Brainfuck was invented by Urban Müller in 1993, in an attempt to make a language for which he could write the smallest possible compiler for the Amiga OS, version 2.0. He managed to write a 240-byte compiler.

Here is a compiler from Brainfuck to Uxn bytecode, it will emit an hexadecimal string that can be copy-pasted back into the interpreter and evaluated natively:

CHIP-8 was created by RCA engineer Joe Weisbecker in 1977 for the COSMAC VIP microcomputer.

The Chip-8 language is capable of accessing up to 4KB(4096 bytes) of RAM, from location 0x000 to 0xFFF(0-4095). The first 512 bytes, from 0x000 to 0x1FF, are where the original interpreter was located, and should not be used by programs.

Registers

Keypad

The computers which originally used the Chip-8 Language had a 16-key hexadecimal keypad.

Screen

The original implementation of the Chip-8 language used a 64x32-pixel monochrome display. Programs may also refer to a group of sprites representing the hexadecimal digits 0 through F. These sprites are 5 bytes long, or 8x5 pixels. The data should be stored in the interpreter area of Chip-8 memory (0x000 to 0x1FF).

Instructions

CHIP-8 instructions are always 2 bytes long and arranged in big-endian order, that is with the most significant byte first. The original implementation of the Chip-8 language includes 36 different instructions, including math, graphics, and flow control functions.

All instructions are 2 bytes long and are stored most-significant-byte first. In memory, the first byte of each instruction should be located at an even addresses. If a program includes sprite data, it should be padded so any instructions following it will be properly situated in RAM.

• nnn or addr - A 12-bit value, the lowest 12 bits of the instruction
• n or nibble - A 4-bit value, the lowest 4 bits of the instruction
• x - A 4-bit value, the lower 4 bits of the high byte of the instruction
• y - A 4-bit value, the upper 4 bits of the low byte of the instruction
• kk or byte - An 8-bit value, the lowest 8 bits of the instruction

set_BCD(Vx)
*(I+0) = BCD(3);
*(I+1) = BCD(2);
*(I+2) = BCD(1);

• Technical Reference
• Chip-8 Roms
• Implementation Tutorial
• Test ROM
• Uxntal Implementation
• C Implementation
• JS Implementation

6502 Assembly is the language used to program the Famicom, BBC Micro and Commodore 64 computers.

This page focuses on the assembly language for the 6502 processor, targetting the Famicom.

Lexicon

Directives are commands you send to the assembler to do things like locating code in memory. They start with . and are indented. This sample directive tells the assembler to put the code starting at memory location $8000, which is inside the game ROM area. Labels are aligned to the far left and have a : at the end. The label is just something you use to organize your code and make it easier to read. The assembler translates the label into an address.

Opcodes are the instructions that the processor will run, and are indented like the directives. In this sample, JMP is the opcode that tells the processor to jump to the MyFunction label. Operands are additional information for the opcode. Opcodes have between one and three operands. In this example the #$FF is the operand:

Comments are to help you understand in English what the code is doing. When you write code and come back later, the comments will save you. You do not need a comment on every line, but should have enough to explain what is happening. Comments start with a ; and are completely ignored by the assembler. They can be put anywhere horizontally, but are usually spaced beyond the long lines.

  .org $8000
MyFunction:                    ; A comment
  LDA #$FF
  JMP MyFunction

Styleguide

Major comments are prefixed with two semi-colons, and minor comments are found at the end of a line on the 32nd column if available. Variables and subroutines are lowercase, constants and vectors are uppercase, and routines are capitalized.

;; Variables

  .enum $0000                  ; Zero Page variables
pos_x                   .dsb 1
pos_y                   .dsb 1
  .ende

;; Constants

SPRITE_Y            .equ $0200
SPRITE_X            .equ $0203

RESET:
  NOP

Forever:
  JMP Forever

NMI:
  RTI

;; Routines

Check_Collision: 
  LDA pos_y
  CMP #$88                     ; Floor is at 32y
  BCC @done
  LDA #$88
  STA pos_y
@done:
  RTS

;; Tables

Table_Name:
  .db $40,$46,$4c,$52,$58,$5e,$63,$68

;; Vectors

  .pad $FFFA
  .dw NMI
  .dw RESET
  .dw 0
  .incbin "src/sprite.chr"

The lin6 linter is used to enfore this style on the various assembly projects found on this site.

Registers

The 6502 handles data in its registers, each of which holds one byte(8 bits) of data. There are a total of three general use and two special purpose registers:

Note: When you use X it adds the value of X to the memory address and uses the 16-bit value at that address to do the write. Whereas when you use Y it adds the value of Y to the address stored in the memory address it's reading from instead. 6502 is little-endian, so $0200 is stored as $00 $02 in memory.

• A: The accumulator handles all arithmetic and logic. The real heart of the system..
• X&Y: General purpose registers with limited abilities..
• SP: The stack pointer is decremented every time a byte is pushed onto the stack, and incremented when a byte is popped off the stack..
• PC: The program counter is how the processor knows at what point in the program it currently is. It’s like the current line number of an executing script. In the JavaScript simulator the code is assembled starting at memory location $0600, so PC always starts there..
• PF: The Processor flag contains 7 bits, each flag live in a single bit. The flags are set by the processor to give information about the previous instruction.

Addressing

The 6502 has 9 major(13 in total) addressing modes, or ways of accessing memory.

Common Opcodes

Compare

The compare instructions set or clear three of the status flags (Carry, Zero, and Negative) that can be tested with branch instructions, without altering the contents of the operand. There are three types of compare instructions:

The CMP instruction supports eight different addressing modes, the same ones supported by the ADC and SBC instructions. Since the X and Y registers function primarily as counters and indexes, the CPX and CPY instructions do not require this elaborate addressing capability and operate with just three addressing modes (immediate, absolute, and zero page).

The compare instructions subtract (without carry) an immediate value or the contents of a memory location from the addressed register, but do not save the result in the register. The only indications of the results are the states of the three status flags: Negative (N), Zero (Z), and Carry (C). The combination of these three flags indicate whether the register contents are less than, equal to (the same as), or greater than the operand "data" (the immediate value or contents of the addressed memory location. The table below summarizes the result indicators for the compare instructions.

The compare instructions serve only one purpose; they provide information that can be tested by a subsequent branch instruction. For example, to branch if the contents of a register are less than an immediate or memory value, you would follow the compare instruction with a Branch on Carry Clear (BCC) instruction, as shown by the following:

Comparing Memory to the Accumulator

  CMP  $20    ; Accumulator less than location $20?
  BCC  THERE
HERE:
  ; No, continue execution here.
THERE:
  ; Execute this if Accumulator is less than location $20.

Use of Branch Instructions with Compare

Math

Modulo

Returns in register A.

Mod:
  LDA $00  ; memory addr A
  SEC
Modulus:  
  SBC $01  ; memory addr B
  BCS Modulus
  ADC $01
  RTS

Division

Rounds up, returns in register A.

Div:
  LDA $00 ; memory addr A
  LDX #0
  SEC
Divide:   
  INX
  SBC $01 ; memory addr B
  BCS Divide
  TXA
  RTS

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